---
title: "Discussion on \"Day 18: Design for Testability (DFT) in VLSI\" | Hashnode"
description: "Discussion on \"Day 18: Design for Testability (DFT) in VLSI\". Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and debug during production. As designs become more complex, DFT techniques help maintain quality and re..."
url: "https://hashnode.com/posts/day-18-design-for-testability-dft-in-vlsi/6765a42e867e4b122e90e636"
---

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# [Day 18: Design for Testability (DFT) in VLSI](https://chip.hashnode.dev/day-18-design-for-testability-dft-in-vlsi?utm_source=hashnode&utm_medium=feed)

Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and debug during production. As designs become more complex, DFT techniques help maintain quality and re...

Dec 20, 2024 · 3 min read · chip.hashnode.dev  
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## Written by

[Chandrakiran G](https://hashnode.com/@Chandrakiran)

@Chandrakiran · Chennai,India

  
[View profile](https://hashnode.com/@Chandrakiran)

On a Journey to Master VLSI Design, FPGA, and Digital Circuits | ECE Student Driven by a Passion for Innovation in Technology 🚀💻🔧📡

✨ A Little About Myself ✨ Hi! I’m Chandrakiran G, a final-year ECE student at St. Joseph’s Institute of Technology, passionate about VLSI design and semiconductor technology. Driven by curiosity and ambition, I’ve been exploring chip design, RTL engineering, and FPGA prototyping, documenting my journey through blogs to simplify complex concepts for learners. I believe that with dedication and the right resources, anyone can excel in any domain. This blog is not just about my growth—it’s about building a community of learners who want to grow together in the world of VLSI and electronics. 🚀

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