--- title: "#verilog articles | Hashnode" description: "Explore 28 articles tagged #verilog on Hashnode. Tutorials, guides, and how-tos from the community." url: "https://hashnode.com/tag/verilog" --- Tag # #verilog 28 posts · 28 followers [Sunny Saini](https://hashnode.com/@fpgadiaries) · [Sep 10](https://hashnode.com/posts/entry-0-why-i-am-learning-fpga-design-from-scratch/6aa2d3558909bde0a44cfb3d) ### [Entry 0: Why I am Learning FPGA Design from Scratch](https://fpgadiaries.hashnode.dev/entry-0-why-i-am-learning-fpga-design-from-scratch?utm_source=hashnode&utm_medium=feed) Follow along as I start FPGA Diaries — a beginner's journey into hardware design with Verilog/VHDL, from logic gates to accelerators. 1 min read · [fpgadiaries.hashnode.dev](https://fpgadiaries.hashnode.dev/entry-0-why-i-am-learning-fpga-design-from-scratch?utm_source=hashnode&utm_medium=feed) [circuitrocks](https://hashnode.com/@circuitrocks) · [Sep 7](https://hashnode.com/posts/no-cpu-no-software-this-neural-net-lives-inside-an-artix-7-fpga/6a9e7e9209b35f67b0c61f04) ### [No CPU, No Software: This Neural Net Lives Inside an Artix-7 FPGA](https://circuitrocks.hashnode.dev/no-cpu-no-software-this-neural-net-lives-inside-an-artix-7-fpga?utm_source=hashnode&utm_medium=feed) No CPU No Software: A Basys 3 FPGA recognizes handwritten digits in half a millisecond with no processor, no OS, and no inference library. 3 min read · [circuitrocks.hashnode.dev](https://circuitrocks.hashnode.dev/no-cpu-no-software-this-neural-net-lives-inside-an-artix-7-fpga?utm_source=hashnode&utm_medium=feed) [Vishwaksen Reddy Dhareddy](https://hashnode.com/@vishwaksen-1) · [Jun 21](https://hashnode.com/posts/building-veridoc/6a380520f9b173e76de48941) ### [Building rtl-aid: CI-Native Documentation for RTL Projects](https://vishwaksen.hashnode.dev/building-veridoc?utm_source=hashnode&utm_medium=feed) rtl-aid is a small documentation and linting toolkit for Verilog and SystemVerilog projects. It generates one Markdown page per RTL module, preserves the human-written description, and keeps the mecha 8 min read · [vishwaksen.hashnode.dev](https://vishwaksen.hashnode.dev/building-veridoc?utm_source=hashnode&utm_medium=feed) [Ramiz Qurbanli](https://hashnode.com/@ramizqurbanli) · [Mar 19](https://hashnode.com/posts/from-zero-to-fpga-engineer-why-we-must-master-chip-design/69bbd9218c55d6eefbd54b59) ### [From Zero to FPGA Engineer: Why We Must Master Chip Design](https://chip.qurbanli.com/from-zero-to-fpga-engineer-why-we-must-master-chip-design?utm_source=hashnode&utm_medium=feed) Master chip design from scratch. This FPGA roadmap covers digital logic, Verilog, and the mission for true technological sovereignty. 4 min read · [chip.qurbanli.com](https://chip.qurbanli.com/from-zero-to-fpga-engineer-why-we-must-master-chip-design?utm_source=hashnode&utm_medium=feed) [Parth Panot](https://hashnode.com/@2005Parth) · [Mar 3](https://hashnode.com/posts/architecture-of-crypto-coprocessor/69a73a1356428acc6f0b90f8) ### [From CPU Instructions to Hardware States: Architecture of a Crypto Coprocessor](https://parthwrites.hashnode.dev/architecture-of-crypto-coprocessor?utm_source=hashnode&utm_medium=feed) This is the introductory article about architecture of crypto coprocessor which I am going to elaborate over next few articles 4 min read · [parthwrites.hashnode.dev](https://parthwrites.hashnode.dev/architecture-of-crypto-coprocessor?utm_source=hashnode&utm_medium=feed) [altCourier](https://hashnode.com/@altCourier) · [Feb 7](https://hashnode.com/posts/in-silicon-axi-basics/6986a867cf6464a4afd69116) ### [In Silicon: AXI Basics](https://couriersandbox.hashnode.dev/in-silicon-axi-basics?utm_source=hashnode&utm_medium=feed) Explore AXI, an ARM protocol. Learn its handshake mechanism and variants: AXI4, AXI4-Lite, and AXI-Stream 8 min read · [couriersandbox.hashnode.dev](https://couriersandbox.hashnode.dev/in-silicon-axi-basics?utm_source=hashnode&utm_medium=feed) [altCourier](https://hashnode.com/@altCourier) · [Feb 3](https://hashnode.com/posts/in-silicon-common-warnings-in-verilog-1/6982157b9e22306e68a7f682) ### [In Silicon: Common Warnings in Verilog (1)](https://couriersandbox.hashnode.dev/in-silicon-common-warnings-in-verilog-1?utm_source=hashnode&utm_medium=feed) Learn about common Verilog warnings, their implications on hardware synthesis, and best practices to address them effectively 4 min read · [couriersandbox.hashnode.dev](https://couriersandbox.hashnode.dev/in-silicon-common-warnings-in-verilog-1?utm_source=hashnode&utm_medium=feed) [altCourier](https://hashnode.com/@altCourier) · [Feb 3](https://hashnode.com/posts/in-silicon-number-systems-and-how-verilog-writes-them/6981fd957ae1be6de643390f) ### [In Silicon: Number Systems and How Verilog Writes Them](https://couriersandbox.hashnode.dev/in-silicon-number-systems-and-how-verilog-writes-them?utm_source=hashnode&utm_medium=feed) Learn about different number systems and how Verilog represents them, focusing on binary, decimal, and hexadecimal systems in digital design 4 min read · [couriersandbox.hashnode.dev](https://couriersandbox.hashnode.dev/in-silicon-number-systems-and-how-verilog-writes-them?utm_source=hashnode&utm_medium=feed) [Ahmad Gazali](https://hashnode.com/@ahmadgaz) · [Feb 2](https://hashnode.com/posts/how-pipelined-cpus-are-designed/6980308fbb2d16c76ee654e0) ### [How Pipelined CPUs are Designed](https://ahmadgaz.hashnode.dev/how-pipelined-cpus-are-designed?utm_source=hashnode&utm_medium=feed) In this article, I'll go over how to design a pipelined processor. The processor implements a Hennessy & Patterson-style MIPS RISC instruction set architecture. I provide some parts of the implementation in SystemVerilog. You can browse the full sour... 16 min read · [ahmadgaz.hashnode.dev](https://ahmadgaz.hashnode.dev/how-pipelined-cpus-are-designed?utm_source=hashnode&utm_medium=feed) [altCourier](https://hashnode.com/@altCourier) · [Feb 1](https://hashnode.com/posts/in-silicon-exceptional-points-in-verilog-1/697e9bae18b49caeff33fc2d) ### [In Silicon: Exceptional Points in Verilog (1)](https://couriersandbox.hashnode.dev/in-silicon-exceptional-points-in-verilog-1?utm_source=hashnode&utm_medium=feed) Moving from C to Verilog? Learn how clocks, non-blocking assignments, inferred latches, and the reg vs wire quirk actually work in hardware. 5 min read · [couriersandbox.hashnode.dev](https://couriersandbox.hashnode.dev/in-silicon-exceptional-points-in-verilog-1?utm_source=hashnode&utm_medium=feed)