--- title: "#vlsi articles | Hashnode" description: "Explore 20 articles tagged #vlsi on Hashnode. Tutorials, guides, and how-tos from the community." url: "https://hashnode.com/tag/vlsi" --- Tag # #vlsi 20 posts · 9 followers [WIOWIZ](https://hashnode.com/@wiowiz) · [Apr 14](https://hashnode.com/posts/rvp/69de31e2345b86c2e03a169d) ### [RVP - Reusable Verification Platform](https://rvp.hashnode.dev/rvp?utm_source=hashnode&utm_medium=feed) RVP generates the environment and simulates it on FSiMX, our proprietary functional simulator, eliminating the need for any third-party dependencies t 2 min read · [rvp.hashnode.dev](https://rvp.hashnode.dev/rvp?utm_source=hashnode&utm_medium=feed) [Shaik Mahammad Hussain](https://hashnode.com/@hussain312) · [Nov 19, 2025](https://hashnode.com/posts/sv-part-1-basics/691de7fd461822a30bbd62b2) ### [SV Part-1 Basics](https://mahammad.hashnode.dev/sv-part-1-basics?utm_source=hashnode&utm_medium=feed) Data Types Pre-defined data types net datypes reg Datatypes reg data types 4 States2 States reg 1 bit default x unsignedint 32 bit default 0 signed integer 32 bit default x signedshortint 16 bit default 0 signed time 64 bit default x uns... 8 min read · [mahammad.hashnode.dev](https://mahammad.hashnode.dev/sv-part-1-basics?utm_source=hashnode&utm_medium=feed) [Jayakrishnan Vr](https://hashnode.com/@JKVR) · [Nov 9, 2025](https://hashnode.com/posts/building-a-flashattention-hardware-tile-with-verilator-exploring-ml-accelerator-microarchitectures/69101efb9c228c8311a7c028) ### [Building a FlashAttention Hardware Tile with Verilator: Exploring ML Accelerator Microarchitectures](https://vlsitryouts.hashnode.dev/building-a-flashattention-hardware-tile-with-verilator-exploring-ml-accelerator-microarchitectures?utm_source=hashnode&utm_medium=feed) Transformers have become the backbone of modern AI models, powering everything from GPT-5 to Gemini and DeepSeek. But at the hardware level, their attention layers are still a challenge — dense, memor 5 min read · [vlsitryouts.hashnode.dev](https://vlsitryouts.hashnode.dev/building-a-flashattention-hardware-tile-with-verilator-exploring-ml-accelerator-microarchitectures?utm_source=hashnode&utm_medium=feed) [OurERP](https://hashnode.com/@ourerp) · [Oct 8, 2025](https://hashnode.com/posts/the-silicon-metamorphosis-redefining-vlsi-careers-in-the-ai-era/68e655530d1c4a9f437887d1) ### [The Silicon Metamorphosis: Redefining VLSI Careers in the AI Era](https://semionics.hashnode.dev/the-silicon-metamorphosis-redefining-vlsi-careers-in-the-ai-era?utm_source=hashnode&utm_medium=feed) The Paradigm Shift: From Backend to Center Stage Remember when VLSI engineers worked in the background while product managers took the spotlight? Those days are gone. The past decade has witnessed a remarkable transformation where silicon architects ... 4 min read · [semionics.hashnode.dev](https://semionics.hashnode.dev/the-silicon-metamorphosis-redefining-vlsi-careers-in-the-ai-era?utm_source=hashnode&utm_medium=feed) [Chandrakiran G](https://hashnode.com/@Chandrakiran) · [Sep 22, 2025](https://hashnode.com/posts/deep-learning-vs-physics-informed-neural-networks-pinns-revolutionizing-vlsi-design/68d158caffc6ee8cd02d4ae0) ### [Deep Learning vs Physics-Informed Neural Networks (PINNs): Revolutionizing VLSI Design](https://chip.hashnode.dev/deep-learning-vs-physics-informed-neural-networks-pinns-revolutionizing-vlsi-design?utm_source=hashnode&utm_medium=feed) The field of Very Large Scale Integration (VLSI) is rapidly evolving with the incorporation of advanced machine learning methods. Among these, Deep Learning (DL) and Physics-Informed Neural Networks (PINNs) have emerged as powerful tools that are tra... 2 min read · [chip.hashnode.dev](https://chip.hashnode.dev/deep-learning-vs-physics-informed-neural-networks-pinns-revolutionizing-vlsi-design?utm_source=hashnode&utm_medium=feed) [Gowrav Bukkapattana Gururaj](https://hashnode.com/@gowravraj) · [Mar 29, 2025](https://hashnode.com/posts/ultimate-vlsi-roadmap-exploring-every-role-in-chip-design/67e75a7ab81c9efef6a59291) ### [Ultimate VLSI Roadmap: Exploring Every Role in Chip Design](https://blog.quasarcommunity.org/ultimate-vlsi-roadmap-exploring-every-role-in-chip-design?utm_source=hashnode&utm_medium=feed) The Ultimate VLSI Roadmap is designed to help students and professionals gain clarity in choosing a role for their future careers. 20 min read · [blog.quasarcommunity.org](https://blog.quasarcommunity.org/ultimate-vlsi-roadmap-exploring-every-role-in-chip-design?utm_source=hashnode&utm_medium=feed) [Divya Sharma](https://hashnode.com/@Divya-Sharma) · [Mar 16, 2025](https://hashnode.com/posts/understanding-fpga/67d6afb835adb4c2e2e81a2b) ### [Understanding FPGA](https://blog-1-fpga.hashnode.dev/understanding-fpga?utm_source=hashnode&utm_medium=feed) FPGA is a well renowned term in VLSI(Very Large Scale Integration) domain. Let’s dive into it and understand it in a simple language. So, here we go…… What is FPGA ? FPGA stands for Field Programmable Gate Array, FPGA is a type of chip that you can r... 2 min read · [blog-1-fpga.hashnode.dev](https://blog-1-fpga.hashnode.dev/understanding-fpga?utm_source=hashnode&utm_medium=feed) [Chandrakiran G](https://hashnode.com/@Chandrakiran) · [Jan 1, 2025](https://hashnode.com/posts/day-23-timing-analysis-and-closure-in-vlsi-design/67757781f545f6681eb91424) ### [Day 23: Timing Analysis and Closure in VLSI Design](https://chip.hashnode.dev/day-23-timing-analysis-and-closure-in-vlsi-design?utm_source=hashnode&utm_medium=feed) Welcome to Day 23! Today, we explore Timing Analysis and Closure, a pivotal step in the VLSI design flow. Timing analysis ensures that the design meets performance requirements, while timing closure fine-tunes the design to resolve timing violations.... 3 min read · [chip.hashnode.dev](https://chip.hashnode.dev/day-23-timing-analysis-and-closure-in-vlsi-design?utm_source=hashnode&utm_medium=feed) [Chandrakiran G](https://hashnode.com/@Chandrakiran) · [Dec 22, 2024](https://hashnode.com/posts/day-20-floorplanning-and-placement-in-vlsi-design/6768267dcb235dcf45b14024) ### [Day 20: Floorplanning and Placement in VLSI Design](https://chip.hashnode.dev/day-20-floorplanning-and-placement-in-vlsi-design?utm_source=hashnode&utm_medium=feed) Welcome to Day 20! Today, I explored Floorplanning and Placement, key stages in the physical design process of VLSI. These steps are fundamental to achieving an efficient and optimized chip layout, balancing performance, area, and power requirements.... 3 min read · [chip.hashnode.dev](https://chip.hashnode.dev/day-20-floorplanning-and-placement-in-vlsi-design?utm_source=hashnode&utm_medium=feed) [Chandrakiran G](https://hashnode.com/@Chandrakiran) · [Dec 20, 2024](https://hashnode.com/posts/day-18-design-for-testability-dft-in-vlsi/6765a42e867e4b122e90e636) ### [Day 18: Design for Testability (DFT) in VLSI](https://chip.hashnode.dev/day-18-design-for-testability-dft-in-vlsi?utm_source=hashnode&utm_medium=feed) Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and debug during production. As designs become more complex, DFT techniques help maintain quality and re... 3 min read · [chip.hashnode.dev](https://chip.hashnode.dev/day-18-design-for-testability-dft-in-vlsi?utm_source=hashnode&utm_medium=feed)