Nivesh Sniveshs.hashnode.dev·Jul 16, 2024Understanding Processors: Types and Key Concepts“The Grid. A digital frontier. I tried to picture clusters of information as they moved through the computer. What did they look like? Ships, motorcycles? Were the circuits like freeways? I kept dreaming of a world I thought I’d never see. And then, ...Discussprocessor
FPGAfpgakey.hashnode.dev·Dec 22, 2023Powering Intelligence at the Edge: Zynq UltraScale+ and the Frontier of Machine Learning IntegrationAs artificial intelligence reshapes industries, the Zynq UltraScale+ series takes center stage in enabling AI at the edge. This article explores how these devices seamlessly integrate with machine learning frameworks, providing a robust platform for ...Discussxilinx
Muhammad Hamza Muneerhamzamuneer.hashnode.dev·Mar 12, 2023Dynamic Partial Reconfiguration in FPGAsPartial Reconfiguration also called Dynamic function exchange (DFX) is used for the partial reconfiguration of the FPGA while the system is still running. This can be useful in situations where a system needs to be updated or modified without interru...Discuss·173 readsxilinx
Muhammad Hamza Muneerhamzamuneer.hashnode.dev·Sep 17, 2022Metastability & Clock Domains in FPGAThis article provides an overview of "Metastability", "Clock Domains", the hazards associated with them and finally the mitigation techniques. Clock Domain Part of the design that is driven by one or more clocks that are related to each other. For ex...Discuss·2 likes·298 readsfpga
Anjan Nairblog.anjann.dev·Aug 10, 2022Xilinx Setup on UbuntuXilinx has been one software used to program the FPGA board in Verilog. Currently (at the time of writing) quite funnily this software fails to install in Windows 11 and has some issues installing in Windows 10. Linux however does not fail us here. T...DiscussUbuntu
ANIL TIRLIOĞLUforasynxasynx.hashnode.dev·Dec 7, 2020Getting started to Vitis acceleration flow with Zynq 7000We all know, sometimes it is just hard to get started learning things from vendor documentations. This tutorial will follow beginner friendly steps to run your first accelerator on an FPGA. ℹ This tutorial will be more beneficial when used in conjun...Discussvitis
Yunus Esergünforasynxasynx.hashnode.dev·Nov 27, 2020MII signal bug in Xilinx FPGAThe main goal of this article to give the general information about Ethernet packets and MII concept, and demonstrate a bug that I have recently faced while working on MII signals in Vivado, with the architecture that I build. General information The...Discussenglish
Yunus Esergünforasynxasynx.hashnode.dev·Oct 21, 2020MIG "init_calib_complete" signal does not go highFor a project, which utilizes 7-Series, I should use PL memory and MIG is the best IP choice for this purpose. In many websites, including Xilinx documents, you can find how to configure MIG IP. Even if there are many configuration parameters in MIG ...Discuss·1 like·65 readsddr
