Shrihari

I am primarily an RTL Design Engineer who can cross boundaries from Micro-architecture to defining novel hardware architectures as well as performing formal verification.

My interests span developing Machine Learning/Cryptographic/Special Function Accelerators, SoC Design, custom FPGA Fabrics, etc., I actively contribute to open-source projects in building the ecosystem around TL-Verilog and developing the associated Design and Verification Flow Methodologies.