✨ A Little About Myself ✨ Hi! I’m Chandrakiran G, a final-year ECE student at St. Joseph’s Institute of Technology, passionate about VLSI design and semiconductor technology. Driven by curiosity and ambition, I’ve been exploring chip design, RTL engineering, and FPGA prototyping, documenting my journey through blogs to simplify complex concepts for learners. I believe that with dedication and the right resources, anyone can excel in any domain. This blog is not just about my growth—it’s about building a community of learners who want to grow together in the world of VLSI and electronics. 🚀
I’m passionate about VLSI Design (CMOS, RTL, Layouts, Optimization), FPGA Development (Xilinx ISE & Vivado), HDL Programming (Verilog/SystemVerilog), and EDA tools (Simulation, Synthesis, STA). I also share learning resources, tutorials, and tech insights to support fellow learners and engineers.
Sep 22, 2025 · 2 min read · The field of Very Large Scale Integration (VLSI) is rapidly evolving with the incorporation of advanced machine learning methods. Among these, Deep Learning (DL) and Physics-Informed Neural Networks (PINNs) have emerged as powerful tools that are tra...
Join discussion
Jan 1, 2025 · 3 min read · Welcome to Day 23! Today, we explore Timing Analysis and Closure, a pivotal step in the VLSI design flow. Timing analysis ensures that the design meets performance requirements, while timing closure fine-tunes the design to resolve timing violations....
Join discussion
Dec 26, 2024 · 3 min read · Welcome to Day 22! Today’s topic is Routing in VLSI Design, an essential step in the physical design flow. Routing establishes electrical connections between components on a chip while meeting performance, power, and area constraints. What is Routin...
Join discussion
Dec 23, 2024 · 3 min read · Welcome to Day 21! Today’s focus is on Clock Tree Synthesis (CTS), a critical step in the VLSI design flow that ensures efficient clock signal distribution across a chip. Proper clock distribution is vital for synchronous operation and avoiding timin...
Join discussion
Dec 22, 2024 · 3 min read · Welcome to Day 20! Today, I explored Floorplanning and Placement, key stages in the physical design process of VLSI. These steps are fundamental to achieving an efficient and optimized chip layout, balancing performance, area, and power requirements....
Join discussion