@verifrushi
Seeking the DV truth, one bit at a time!
Nothing here yet.
Mar 7 · 4 min read · In SystemVerilog, the difference between static and automatic isn't just about syntax; it’s about where and when your data exists in the simulator's memory. In modern high-performance CPU DV, getting
Join discussionMar 6 · 4 min read · In our previous journey, we saw how a Parent handle can point to a Child object on the heap. But there’s a catch: by default, SystemVerilog is blind to the Child’s specialized methods if you use a Par
Join discussionMar 6 · 3 min read · Every Child is a Parent, but Not Every Parent is a Child! In the Infinite Ocean of Design Verification, we often get lost in the waves of complex UVM macros. But to navigate the deep waters of CPU an
Join discussion
