compilercodegen.hashnode.devLLVM Instruction Selection: Pattern Matching in ISelDAGToDAGThis is some of my notes for LLVM's ISelDAGToDAG instruction selector and how SelectionDAG patterns are matched and lowered to machine instructions. Purpose What: ISelDAGToDAG translates a legalized SelectionDAG into target-specific machine instruct...Aug 9, 2025·8 min read
compilercodegen.hashnode.devLLVM Instruction Selection: Legalization Pass Deep DiveThis article is a follow-up to my previous post LLVM Instruction Selection: SelectionDAG Building, where we explored how SelectionDAGs are constructed from LLVM IR. In this post, we explore the next phase: legalization*, which ensures the DAG conform...Jun 29, 2025·6 min read
compilercodegen.hashnode.devLLVM Instruction Selection: SelectionDAG BuildingLLVM's instruction selection (ISel) is a key stage in the LLVM backend that translates high-level LLVM IR into target-specific machine instructions. This post focuses on the frontend of instruction selection—the phase that builds the SelectionDAG fro...Jun 20, 2025·4 min read
my-tvm-from-scratch-1.hashnode.devTowards a minimal compiling example (1): PassContextWhat Is PassContext? A PassContext is a contextual object that exists during the execution of IR passes. It acts as a shared environment to configure and control the behavior of optimization passes without hard-coding logic into each one. If you’re f...Apr 8, 2025·3 min read
my-tvm-from-scratch-1.hashnode.devBuilding a Minimal IR for ONNX Model Compilation: From Concept to ImplementationIntroduction: The Role of Intermediate Representations Our compiler's Intermediate Representation (IR) serves as the crucial bridge between high-level ONNX models and optimized executable code. This post documents my implementation of a minimal Relay...Jan 27, 2025·4 min read