From Cameroon to Cloud Engineering at ISAE-SUPAERO/ENSEEIHT |DeepTech & Distributed Systems
Hi, I'm Nathanael. MSc graduate from Toulouse INP - ENSEEIHT (N7), France. I work on hardware/software co-design and low-level performance. I just completed a six-month research internship at INRIA Rennes, where I designed a hardware isolation mechanism for processing-in-memory processors (UPMEM), measured in a cycle-accurate simulator at 5.54% overhead at most, against 26 to 120% for a software scheme, and validated on FPGA. I write about computer architecture, operating systems, networking (RDMA/InfiniBand) and the move from research to industry. I am looking for my first role in systems and performance engineering, AI infrastructure or low-level software. Stack: C/C++, Go, Python, Verilog, Linux, RDMA, Terraform, Ansible. Contact: nathanaelfetuefoko@gmail.com | linkedin.com/in/nathanael-fetue-foko | github.com/NathanaelFetue
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c-wind
The distinction between CQ completion and remote delivery makes the perftest comparison much clearer. One reproducibility detail that could help interpret the 7.7 µs event-vs-poll median delta is whether the submitting thread and IRQ/NIC processing were CPU-pinned; even on Soft-RoCE, scheduler placement can shift that wake-up cost. Your caveat about the three-vCPU VM and noisy maxima already points to why it matters.