Ssumitsomani94insumitsomani.hashnode.dev·Apr 19 · 4 min readUnder the Hood of PCIe: BARs, Config Spaces, and SwitchesPost 1.2 in the Advanced Systems Validation Series) In our previous post, we mapped the 7-step journey of an NVMe command. We established that the Host CPU must physically write to a "Doorbell Registe00
Ssumitsomani94insumitsomani.hashnode.dev·Apr 19 · 5 min readDeep Dive: The Full-Stack NVMe Journey (Macro to Micro)(Post 1.1 in the Advanced Systems Validation Series) When you are testing NVMe SSD Controllers in an enterprise validation lab, understanding the theoretical speed of storage is only half the battle. 00
Ssumitsomani94insumitsomani.hashnode.dev·Apr 18 · 3 min readThe Birth of NVMe: When Software Finally Caught Up(Post 0.3 in the Advanced Systems Validation Series) In our last post, we saw how hardware engineers connected storage directly to the CPU via the massive, multi-lane PCIe superhighway. But even thoug00
Ssumitsomani94insumitsomani.hashnode.dev·Apr 18 · 3 min readThe Traffic Jam Inside Your PC: Why Storage Required the PCIe Highway(Post 0.2 in the Advanced Systems Validation Series) If you read the previous post on the Memory Hierarchy, you know that the CPU (The Chef) must fetch all of its data from Storage (The Fridge) and pl00
Ssumitsomani94insumitsomani.hashnode.dev·Apr 18 · 3 min readThe Hardware Hierarchy: Why Your CPU Needs Both Memory and StorageBy Sumit Somani | Staff Validation Engineer As a Validation Engineer working on next-generation NVMe and CXL hardware, I spend my days looking at how data moves. But before we can talk about advanced 00
