SSaguninsagunwrites.hashnode.dev·Aug 16 · 7 min readTypes of CPU OrganizationThe CPU is responsible for executing instructions and processing data. But CPUs don't all organize their registers, operands, and data paths in the same way. Different designs use different methods to00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readBase Register Addressing ModeIn the previous article, we learned about Relative Addressing, where the CPU calculates an address using a reference address and an offset. Now we'll learn about Base Register Addressing. This address00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 7 min readRelative Addressing ModeIn the previous article, we learned about Indirect Addressing, where the instruction leads to an address that contains the actual address of the operand. Now we'll learn about Relative Addressing Mode00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 9 min readAddressing ModesA CPU instruction tells the processor what operation to perform. But when an instruction needs data, another question appears: Where is that data located? The method used by an instruction to specify 00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readSingle Accumulator OrganizationIn the previous article, we introduced the major types of CPU organization. Now we'll examine the first one in detail: Single Accumulator Organization. The accumulator-based organization is one of the00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readIndexed Addressing ModeIn the previous article, we learned about Base Register Addressing, where the CPU combines a base address with an offset to find the effective address. Now we'll learn about Indexed Addressing Mode, w00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readRegister Indirect Addressing ModeIn the previous article, we learned about Register Addressing, where the operand is stored directly inside a CPU register. Now we're going one level deeper. In Register Indirect Addressing, the regist00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 8 min readMemory Stack OrganizationIn the previous article, we learned about Register Stack Organization, where the active elements of a stack are stored in CPU registers. But registers have limited capacity. So how can a CPU maintain 00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 5 min readRegister Addressing ModeIn the previous article, we learned about Immediate Addressing Mode, where the operand value is included directly inside the instruction. Now we'll look at another common addressing mode: Register Add00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 5 min readArithmetic InstructionsComputers are constantly performing calculations. Adding numbers, subtracting values, increasing counters, and comparing numerical quantities are all common operations performed by a processor. The CP00
