SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readIndexed Addressing ModeIn the previous article, we learned about Base Register Addressing, where the CPU combines a base address with an offset to find the effective address. Now we'll learn about Indexed Addressing Mode, w00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 7 min readRelative Addressing ModeIn the previous article, we learned about Indirect Addressing, where the instruction leads to an address that contains the actual address of the operand. Now we'll learn about Relative Addressing Mode00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readIndirect Addressing ModeIn the previous article, we learned about Direct Addressing, where the instruction directly contains the memory address of the operand. Now we'll take one extra step. In Indirect Addressing, the addre00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 6 min readDirect Addressing ModeIn the previous article, we learned how Auto-Increment and Auto-Decrement Addressing can automatically modify a register while accessing memory. Now we'll look at Direct Addressing Mode, where the mem00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 5 min readRegister Addressing ModeIn the previous article, we learned about Immediate Addressing Mode, where the operand value is included directly inside the instruction. Now we'll look at another common addressing mode: Register Add00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 5 min readImmediate Addressing ModeIn the previous article, we learned about Implied Addressing, where the operand is automatically understood from the instruction. Now we'll look at another simple addressing mode: Immediate Addressing00
SSaguninsagunwrites.hashnode.dev·Aug 16 · 4 min readImplied Addressing ModeIn the previous article, we introduced addressing modes and learned that they describe how a CPU finds the operand required by an instruction. We'll now study each addressing mode individually, starti00
