Feb 3 · 8 min read · Introduction In the previous two posts, I explored why execution-driven simulation is essential for modeling modern processors and analyzed Issue #14 from the Olympia repository, which calls for adding execution-driven support. That discussion reveal...
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Jan 31 · 7 min read · Introduction In my previous post, I explored the motivation behind execution-driven performance modeling and how Olympia currently operates as a trace-driven simulator. This post builds directly on that foundation by analyzing Issue #14: “Add executi...
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Jan 30 · 6 min read · BIP110 Soft Fork Progress: ~4.7 % Node Support, Mining Pools Absent BIP110 was proposed in early December 2025, introducing a temporary, consensus-level limit on the amount of data transmitted in transactions, aimed at mitigating spam. According to d...
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Jan 30 · 2 min read · BIP110 软分叉进展：约 4.7 % 节点支持，矿池尚未跟进 BIP110 于 2025 年 12 月初提出，建议对交易中传输的数据大小设定临时共识级别限制，旨在打击垃圾邮。根据 BitcoinPortal 数据，截至 1 月 30 日，比特币区块链中 23217 个节点中有 1097 个（~4.7%） 支持 BIP110 软分叉。支持仅来自运行 Bitcoin Knots 的节点，而前 20 大矿池尚未发出任何支持信号。 QRAMP：两阶段“隔离模式”优化后量子迁移 比特币开发者 Bnav...
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Jan 28 · 9 min read · The Beginning: A Challenge Wrapped in an Opportunity Pushing the SpacemiT K3 to the Limit: Vectorizing AudioMark for RISC-V" When I started exploring RISC-V Vector extension (RVV) optimization, I had no idea I'd end up spending weeks wrestling with v...
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Jan 27 · 10 min read · Introduction Performance modeling plays a critical role in modern processor design. Before committing designs to silicon, architects rely on performance models to explore micro-architectural trade-offs, evaluate bottlenecks, and predict behavior unde...
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Jan 21 · 9 min read · Introduction: The Mission The target: EEMBC AudioMark — an industry-standard benchmark that simulates a real-world audio pipeline with beamforming, echo cancellation, noise reduction, and keyword spotting. It's the perfect testbed for DSP optimizati...
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Jan 19 · 8 min read · First why RISC-4? Well why not? Ok so actually though I do realize that RISC-v(5) is named for it being the fifth major iteration of the RISC isa. But there is no RISC-4 or RISC-IV, I didn’t want to use numerals because of the possibility of confusio...
Join discussionNov 10, 2025 · 4 min read · If you’ve been following recent developments in system software, you might have noticed a pattern emerging. On the surface, stories about formal verification, reproducible builds, and non-root CI pipelines can seem like niche topics. But when you loo...
Join discussionAug 11, 2025 · 4 min read · 1. Background & Motivation Modern RISC-V SoC development often demands parallel hardware and firmware progress. Waiting for RTL completion or silicon fabrication delays firmware bring-up and can mask integration bugs until late in the project. Tradit...
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