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SMShaik Mahammad Hussainmahammad.hashnode.devNov 19, 2025 · 8 min read

SV Part-1 Basics

Data Types Pre-defined data types net datypes reg Datatypes reg data types 4 States2 States reg 1 bit default x unsignedint 32 bit default 0 signed integer 32 bit default x signedshortint 16 bit default 0 signed time 64 bit default x uns...

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JVJayakrishnan Vrvlsitryouts.hashnode.devNov 9, 2025 · 5 min read

Building a FlashAttention Hardware Tile with Verilator: Exploring ML Accelerator Microarchitectures

Transformers have become the backbone of modern AI models, powering everything from GPT-5 to Gemini and DeepSeek. But at the hardware level, their attention layers are still a challenge — dense, memory-bound, and hard to accelerate efficiently. In th...

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OOurERPsemionics.hashnode.devOct 8, 2025 · 4 min read

The Silicon Metamorphosis: Redefining VLSI Careers in the AI Era

The Paradigm Shift: From Backend to Center Stage Remember when VLSI engineers worked in the background while product managers took the spotlight? Those days are gone. The past decade has witnessed a remarkable transformation where silicon architects ...

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CGChandrakiran Gchip.hashnode.devSep 22, 2025 · 2 min read

Deep Learning vs Physics-Informed Neural Networks (PINNs): Revolutionizing VLSI Design

The field of Very Large Scale Integration (VLSI) is rapidly evolving with the incorporation of advanced machine learning methods. Among these, Deep Learning (DL) and Physics-Informed Neural Networks (PINNs) have emerged as powerful tools that are tra...

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GBGowrav Bukkapattana Gururajblog.quasarcommunity.orgMar 29, 2025 · 20 min read

Ultimate VLSI Roadmap: Exploring Every Role in Chip Design

Introduction This blog is designed for students seeking a complete roadmap of chip design in the industry. While I won’t be teaching subjects here, if you have basic knowledge of VLSI and electronics, you can use this blog to gain clarity on the care...

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DSDivya Sharmablog-1-fpga.hashnode.devMar 16, 2025 · 2 min read

Understanding FPGA

FPGA is a well renowned term in VLSI(Very Large Scale Integration) domain. Let’s dive into it and understand it in a simple language. So, here we go…… What is FPGA ? FPGA stands for Field Programmable Gate Array, FPGA is a type of chip that you can r...

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CGChandrakiran Gchip.hashnode.devJan 1, 2025 · 3 min read

Day 23: Timing Analysis and Closure in VLSI Design

Welcome to Day 23! Today, we explore Timing Analysis and Closure, a pivotal step in the VLSI design flow. Timing analysis ensures that the design meets performance requirements, while timing closure fine-tunes the design to resolve timing violations....

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CGChandrakiran Gchip.hashnode.devDec 22, 2024 · 3 min read

Day 20: Floorplanning and Placement in VLSI Design

Welcome to Day 20! Today, I explored Floorplanning and Placement, key stages in the physical design process of VLSI. These steps are fundamental to achieving an efficient and optimized chip layout, balancing performance, area, and power requirements....

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CGChandrakiran Gchip.hashnode.devDec 20, 2024 · 3 min read

Day 18: Design for Testability (DFT) in VLSI

Welcome to Day 18! Today’s focus was on Design for Testability (DFT), an essential aspect of VLSI design aimed at ensuring chips are easy to test and debug during production. As designs become more complex, DFT techniques help maintain quality and re...

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CGChandrakiran Gchip.hashnode.devDec 16, 2024 · 3 min read

Day 14: Advanced Floorplanning Strategies in VLSI Design

Welcome to Day 14! Today’s focus was on advanced floorplanning techniques, an essential step in the physical design flow that significantly impacts chip performance, power, and manufacturability. Floorplanning becomes especially critical in handling ...

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Trending tags this week

SV Part-1 Basics

Building a FlashAttention Hardware Tile with Verilator: Exploring ML Accelerator Microarchitectures

The Silicon Metamorphosis: Redefining VLSI Careers in the AI Era

Deep Learning vs Physics-Informed Neural Networks (PINNs): Revolutionizing VLSI Design

Ultimate VLSI Roadmap: Exploring Every Role in Chip Design

Understanding FPGA

Day 23: Timing Analysis and Closure in VLSI Design

Day 20: Floorplanning and Placement in VLSI Design

Day 18: Design for Testability (DFT) in VLSI

Day 14: Advanced Floorplanning Strategies in VLSI Design