#rtl articles | Hashnode

MJManiruzzaman Jubayerjubayer910.hashnode.dev3d ago · 19 min read

RTL UI design for Arabic apps: a guide for UAE teams

Originally published at maniruzzamanjubayer.com. RTL UI design for Arabic apps comes down to one rule and a few exceptions. Mirror everything that follows reading order or shows forward motion: layout

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AAbdulrahmanamlaki.hashnode.devSep 24 · 7 min read

Building an Arabic-First SaaS: Seven Real Technical Challenges from the Saudi Market

"Arabic-first" is not a language setting added at the end of a project. It is an architectural decision that touches the presentation layer, the data layer, and the calculation layer at once. The diff

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VRVishwaksen Reddy Dhareddyvishwaksen.hashnode.devJun 21 · 8 min read

Building rtl-aid: CI-Native Documentation for RTL Projects

rtl-aid is a small documentation and linting toolkit for Verilog and SystemVerilog projects. It generates one Markdown page per RTL module, preserves the human-written description, and keeps the mecha

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WWIOWIZvai-virtual-ai-inference.hashnode.devJan 25 · 4 min read

VAI: Zero-Overhead Model Switching for AI Inference

published: trueDescription: "Why we treat model weights like ROM, not malloc()" The Problem Every time you switch models in a typical inference setup: 1. Unload weights from GPU memory 2. Load new weights from disk 3. Rebuild execution state 4. Warm ...

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SGSaurabh Guptacodecraft-by-saurabh.hashnode.devDec 21, 2025 · 5 min read

How I Learned Unit Testing with React Testing Library (RTL) by Implementing It in a Real Project

For a long time, unit testing was the most ignored part of my React learning journey. Not because I didn’t care about quality — but because testing always felt abstract.Most tutorials showed isolated examples that didn’t resemble real applications. S...

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SMShaik Mahammad Hussainmahammad.hashnode.devNov 19, 2025 · 8 min read

SV Part-1 Basics

Data Types Pre-defined data types net datypes reg Datatypes reg data types 4 States2 States reg 1 bit default x unsignedint 32 bit default 0 signed integer 32 bit default x signedshortint 16 bit default 0 signed time 64 bit default x uns...

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JVJayakrishnan Vrvlsitryouts.hashnode.devNov 9, 2025 · 5 min read

Building a FlashAttention Hardware Tile with Verilator: Exploring ML Accelerator Microarchitectures

Transformers have become the backbone of modern AI models, powering everything from GPT-5 to Gemini and DeepSeek. But at the hardware level, their attention layers are still a challenge — dense, memor

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APAbheeshta Pabheeshta-beyond-webstacks.hashnode.devAug 25, 2025 · 5 min read

Jest & React Testing Library (RTL) – Simplified

Testing is not just about verifying if code runs. It’s about verifying that your app behaves correctly from the user’s perspective. Jest + React Testing Library (RTL) gives a powerful combination to achieve this. 1. Filtering Tests in Watch Mode When...

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SXShuran Xuembeddedville.hashnode.devAug 11, 2025 · 4 min read

SW/HW Co-Simulation Stack Design

1. Background & Motivation Modern RISC-V SoC development often demands parallel hardware and firmware progress. Waiting for RTL completion or silicon fabrication delays firmware bring-up and can mask integration bugs until late in the project. Tradit...

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AKAlim Khandeveloperblogg.hashnode.devAug 25, 2024 · 1 min read

Jest Roadmap.

Over the past few weeks, I’ve been diving into Jest to use in a company project. To quickly get up to speed with the syntax, I followed this YouTube tutorial. Afterward, I practiced by writing some code and uploaded it to GitHub. You can check it out...

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