Mar 3 · 4 min read · Last semester, I had an Information Security course, in which we went from the basics like Caesar ciphers all the way to modern algorithms like AES and SHA-256. Naturally, being a dev, I got curious a
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Feb 3 · 4 min read · In C, when the compiler warns you about an unused variable or an implicit conversion, you can shrug it off and the program runs fine. The warning might point to sloppy code, but the CPU does not care. It executes what you wrote. Verilog is different....
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Feb 3 · 4 min read · When you ask a person who is not particularly interested in mathematics what other number systems exist, probably they won’t expect there to be any. Human Way: Decimal As humans, we start off by counting with our fingers that is from 1 to 10 given a ...
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Feb 2 · 16 min read · In this article, I'll go over how to design a pipelined processor. The processor implements a Hennessy & Patterson-style MIPS RISC instruction set architecture. I provide some parts of the implementation in SystemVerilog. You can browse the full sour...
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Feb 1 · 5 min read · The first thing to realize when moving from C to Verilog is that you are no longer writing a script but instead describing a physical hardware. The action of code evolves from being a recipe into being a blueprint. And this evolution happens with lea...
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Nov 14, 2025 · 3 min read · You don’t actually “select FPGA pins” inside Verilog – you name ports in Verilog, and then you map those ports to physical pins using a constraints file (or pin planner GUI) in your FPGA tools. Think of it as: Verilog = logical signalsConstraints (X...
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Sep 26, 2025 · 5 min read · Hardware Description Languages (HDLs) like Verilog and VHDL configure FPGAs by describing digital circuits that are then synthesized, placed, and routed onto the FPGA fabric. Here's the complete process: 1. HDL Code Describes Behavior Basic Gate-Leve...
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