SSunny Saini·Sep 10Entry 0: Why I am Learning FPGA Design from Scratch Follow along as I start FPGA Diaries — a beginner's journey into hardware design with Verilog/VHDL, from logic gates to accelerators.1 min read·fpgadiaries.hashnode.dev
Ccircuitrocks·Sep 7No CPU, No Software: This Neural Net Lives Inside an Artix-7 FPGANo CPU No Software: A Basys 3 FPGA recognizes handwritten digits in half a millisecond with no processor, no OS, and no inference library.3 min read·circuitrocks.hashnode.dev
VVishwaksen Reddy Dhareddy·Jun 21Building rtl-aid: CI-Native Documentation for RTL Projects rtl-aid is a small documentation and linting toolkit for Verilog and SystemVerilog projects. It generates one Markdown page per RTL module, preserves the human-written description, and keeps the mecha8 min read·vishwaksen.hashnode.dev
RRamiz Qurbanli·Mar 19From Zero to FPGA Engineer: Why We Must Master Chip DesignMaster chip design from scratch. This FPGA roadmap covers digital logic, Verilog, and the mission for true technological sovereignty.4 min read·chip.qurbanli.com4
PParth Panot·Mar 3From CPU Instructions to Hardware States: Architecture of a Crypto CoprocessorThis is the introductory article about architecture of crypto coprocessor which I am going to elaborate over next few articles4 min read·parthwrites.hashnode.dev
AaltCourier·Feb 7In Silicon: AXI BasicsExplore AXI, an ARM protocol. Learn its handshake mechanism and variants: AXI4, AXI4-Lite, and AXI-Stream8 min read·couriersandbox.hashnode.dev
AaltCourier·Feb 3In Silicon: Common Warnings in Verilog (1)Learn about common Verilog warnings, their implications on hardware synthesis, and best practices to address them effectively4 min read·couriersandbox.hashnode.dev
AaltCourier·Feb 3In Silicon: Number Systems and How Verilog Writes ThemLearn about different number systems and how Verilog represents them, focusing on binary, decimal, and hexadecimal systems in digital design4 min read·couriersandbox.hashnode.dev
AAhmad Gazali·Feb 2How Pipelined CPUs are DesignedIn this article, I'll go over how to design a pipelined processor. The processor implements a Hennessy & Patterson-style MIPS RISC instruction set architecture. I provide some parts of the implementation in SystemVerilog. You can browse the full sour...16 min read·ahmadgaz.hashnode.dev
AaltCourier·Feb 1In Silicon: Exceptional Points in Verilog (1)Moving from C to Verilog? Learn how clocks, non-blocking assignments, inferred latches, and the reg vs wire quirk actually work in hardware.5 min read·couriersandbox.hashnode.dev
